✦ Packaging: CoWoS, CoPoS & the Second MoatNarrow moat

Every AI accelerator that matters is not just fabbed but assembled by TSMC — GPUs and memory stacked on interposers through CoWoS — and that assembly step has been the binding constraint of the AI boom. The response is a second moat under construction: capacity driving toward roughly 130,000 wafers a month by late 2026, nearly four times late-2024 levels, with the supply-demand gap narrowing from about 20% to 10% by year-end¹. Beyond CoWoS waits CoPoS — panel-level packaging with pilot production targeted for 2027 — and an overflow system routing hundreds of thousands of wafers to partners like Amkor and SPIL.

The wager inside the expansion: packaging is where TSMC's process lead converts into system-level lock-in, because a customer who fabs at TSMC and packages at TSMC has nowhere else to take the finished design. The risk is the classic capacity trap — quadrupling a chokepoint is glorious until demand pauses, at which point it is empty cleanrooms at $60-64 billion of annual capex². Watch the gap closing on schedule and utilization staying tight as the new lines land.