⚠ A Node That Arrives Late Is a Year of Expensive BitsModerate threat

Sandisk (SNDK) — threat to the moat

A generation arriving a year late in NAND is a year of selling more expensive bits than everyone else, and Sandisk cannot accelerate one alone.

A node that arrives late in NAND is not a delay, it is a year of selling more expensive bits than the competition.

Where a node transition can slipStructureThree bonded 100+ layer strings, not a monolithYieldOn a stacked, bonded dieFabK2 conversion at KitakamiInterface4.8 Gbit/s, Toggle DDR6.0 with SCASandisk can accelerate aloneNoCost of a year lateA year of more expensive bitsCadence has been about two years for eight generations. Three would put Sandisk a full node behind.
A delayed node in NAND is not an inconvenience — it is a structurally higher cost on an identical product.

The roadmap is credible and it is a schedule rather than a fact. BiCS10 at 332 layers is sample shipping with mass production expected in 2027 at Kitakami, using a three-string bonded structure rather than a monolithic stack.1 Every element of that — the bonding, the yield on three stacked strings, the K2 fab conversion, the 4.8 Gbit/s interface — is a place where a semiconductor programme can lose two quarters.

The competitive cost of slipping is unusually direct here because NAND has no product differentiation to hide behind. Cost per bit follows bits per wafer follows layers. A competitor a generation ahead has a structurally lower cost on an identical product and can price accordingly, which is the mechanism by which memory downturns kill the laggard rather than the market.

Sandisk carries a second-order version of the same risk: it cannot accelerate alone. The node arrives when Flash Ventures brings it, and Flash Ventures is a joint decision with a partner whose priorities are its own.

The record is reassuring. Eight generations, roughly one every two years, with 218-layer BiCS8 in volume and the ninth and tenth already sampling.

Watch the interval between generations rather than the layer count. Two years has been the cadence; three would put Sandisk a full node behind Samsung, and there is no way to earn that back.

References
  1. ReportedBiCS10 at 332 layers is sample shipping with mass production expected in 2027 at Kitakami, using a three-string bonded structure rather than a monolithic stack. Every element of that — the bonding, the yield on three stacked strings, the K2 fab conversion, the 4.8 Gbit/s interface — is a place where a semiconductor programme can lose two quarters.
    Coverage of Kioxia and Sandisk's BiCS10 3D NAND. BiCS10 is a 332-layer technology; the interface speed of 4.8 Gbit/s is 33 percent faster than BiCS8, achieved using the Toggle DDR6.0 interface and a Separate Command Address protocol. Mass BiCS10 production is expected to start in 2027 at the Kitakami plant 2 in Iwate Prefecture, Japan, and because Sandisk and Kioxia share the output of the fab through their joint venture both are sample shipping BiCS10 chips; a QLC version of the 332-layer technology would increase chip capacity by a third. The BiCS10 technology involves stacking three 100-plus layer NAND strings together rather than building a monolithic 332-layer chip. Kioxia has an intervening BiCS9 technology which uses BiCS8 218-layer 3D NAND cells with a separate CMOS logic layer providing more performance than the BiCS8 logic circuitry. For comparison, SK hynix has 321 layers in its ninth-generation 3D NAND, also using a triple string stack design; Samsung has 400 layers with its tenth-generation V-NAND, made with separate logic and NAND cell wafers producing a 1 Tbit die in what Samsung calls a Cell-on-Periphery architecture; Micron is at the 276-layer level; and China's YMTC is expected to announce 300-layer class technology. — 2026 · publ. 2026-07-03 · source ↗
Sources
Generated September 23, 2026