⚠ Late Once Is EnoughHigh threat
Marvell Technology (MRVL) — threat to the moat
Module designs freeze for a generation, so the penalty for arriving second is a cliff, not a slope.
Marvell's optical position was not won by being cheaper. It was won by being earliest at each speed grade — first to 200G-per-lane 1.6T silicon in 5nm with Nova, then the 3nm Ara platform1 — at a moment when module makers had to commit to a supplier before their own products existed.
That advantage is real and it is renewed from zero at every transition. Module designs lock early, they lock for a generation, and the vendor with working silicon on the bench when the design is frozen takes the socket. There is no partial credit for arriving three months later with a better part; the design is already closed.
Which means the franchise is only ever one slipped generation from a step down. Broadcom is targeting the same 3nm, 200G-per-lane ground, and a single missed schedule at 3.2T would hand it a generation's worth of designs that then persist for years. The failure mode is not gradual share loss — it is a cliff at a date.
So watch schedules rather than share. Specifically: whether Marvell samples and ships at the next speed grade ahead of Broadcom, and whether the module makers designing at that grade name it. Share data arrives two years after the decision that caused it.
- Third-party estimateMarvell was first to 200G-per-lane 1.6T in 5nm (Nova), then the 3nm Ara platform; Broadcom's Sian3 targets the same ground.Third-party analysis of the high-speed optical DSP market — Marvell and Broadcom together hold more than 90% of the PAM4 DSP market; within it Marvell holds roughly 60-70% against Broadcom's approximately 30%; Marvell was first to 200G-per-lane 1.6T silicon in 5nm (Nova, 2023) followed by the 3nm Ara platform, and Broadcom's Sian3 targets the same 3nm 200G-per-lane ground — 2026 · publ. 2026 · source ↗