⚠ The Physical Limits of LithographyModerate threat

ASML's technology moat rests on a premise that has held for decades but cannot hold forever: that chips keep advancing by printing ever-smaller features, and that ASML's research keeps finding a way to print them. At some point the physics approaches hard limits — features cannot shrink below the size of atoms — and the cost and difficulty of each further step rise steeply. If lithography-driven scaling slows or stalls, the engine of ASML's perpetual upgrade cycle loses some of its force, and the relentless need for the next, more expensive machine could ease.

The related risk is that the industry advances chips through means that depend less on ASML's ever-finer lithography — advanced packaging, chiplets, three-dimensional stacking, new transistor architectures, or entirely novel computing approaches. Much of the recent progress in AI chips has come as much from packaging and architecture as from raw lithographic shrinking, and a world where performance gains come increasingly from these other techniques is one where ASML remains essential but perhaps less singularly decisive. None of this is near — EUV and High-NA have a long runway, and ASML is itself involved in the adjacent technologies — and the company's research has repeatedly found ways past supposed walls. But the deepest long-term question over the technology moat is whether the game of 'print smaller' continues indefinitely, and physics guarantees that, eventually, it does not — which is why the ~€350 million High-NA machines exist: to keep the shrink going a while longer¹.